Get a Quick Online Quote: Register or Login

Impedance Control and Its Importance in Today’s Designs

In today’s applications where designs are commonly becoming faster and faster, controlling layout parameters is more critical than ever.

There are several ways to approach impedance control during PCB design and production. The most common way is to annotate the information inside the schematic with symbols and special notes, incorporate these notes and design rules when laying out the PCB, and describe it via a PCB fabrication drawing so that your PCB vendor knows about it and can fabricate it appropriately.

Get your PCBs Built-Fast.

Email us for a PCB quote
or call us at 1-800-SFC-5143

Why is it necessary? Simply put, a signal with a given amount of energy and speed will leave a component’s output pin, travel through a PCB trace and end at another component’s input pin.

If the signal’s energy is not fully absorbed by the receiving end, some of the left-over energy can be reflected back onto the trace and travel back to the output pin. These reflections may cause interference with the real signal and lessen the overall signal integrity.

For very short traces, you may not need to worry about controlling impedance but, as a general rule of thumb, any traces longer than 1/10th the wavelength of the signal should incorporate some sort of controlled impedance.

Another general rule of thumb is to incorporate controlled impedance on a trace whose length is longer than 1/3 the rise time of the signal. High Speed USB, Ethernet, DDR Memory, and other low-voltage, differential communication systems are examples of data rates at which require impedance control.

A trace has several characteristics to consider: height, width, length, distance between itself and other copper features (including copper layers beneath or on top of the signal layer containing controlled impedance), the dielectric constant, PCB fabrication tolerances/limits, etc. All of these are considered when calculating and designing for controlled impedance. Most industry-standard CAD software has impedance control and differential pair feature sets that calculate these things for you (and even simulations that can show you expected signal integrity and any potential issues), but knowing how they all play together can help better understand when it is necessary or not.

Here is a screenshot from Altium Designer (taken from Altium TechDocs) on a 4-layer board containing some simple 70-ohm impedance-driven trace widths:

PCB impedance control

These days, controlling impedance is typically done at the board house with modelling software and testing impedance on bare boards upon production, but knowing how to call these specifications out in a drawing is important for the PCB designer as well.

This can usually be accomplished by annotating the PCB drawing with a note and arrow pointing to the trace (or group of traces) on the board, stating that “7mil width and 8mil space layers 1 and 8 require differential impedance of 90 Ohms”, along with the layer stack-up legend and its requirements regarding copper thickness and dielectrics.

IPC Class 2 vs. Class 3 PCBs: What's the Difference?

PCB School

IPC Class 2 vs. Class 3 PCBs: What's the Difference?

When designing a printed circuit board, one of the first decisions is choosing the appropriate IPC class. Specifying IPC Class 2 or Class 3 affects far more than a PCB's inspection criteria. The class chosen influences how the board is designed, fabricated, tested, and accepted throughout the manufacturing process. It also has a direct impact on cost, lead time, and the number of fabricators capable of producing the board.

Read More

Military Grade PCB Specifications: What They Actually Mean in Manufacturing

PCB School

Military Grade PCB Specifications: What They Actually Mean in Manufacturing

Standards like MIL-PRF-55110, MIL-PRF-50884, and MIL-PRF-31032 exist to enforce reliability, traceability, and performance in environments where failure isn't acceptable.

Read More

Flying Probe Testing

PCB School

Flying Probe Testing

Flying probe testing has been the golden standard of functional testing for low volume, prototype runs since the late 80s and 90s. It effectively flips the approach of the traditional in-circuit (ICT) bed-of-nails fixture test, where a custom-built frame with hundreds of spring-loaded pins contact test points simultaneously.

Read More

Double-Sided BGA Assembly

PCB School

Double-Sided BGA Assembly

Double-sided Ball Grid Array (BGA) assembly maximizes component density without increasing board size, enabling high-performance designs for applications ranging from smartphones and IoT devices to medical and industrial electronics.

Read More

PCBA Press Fit Connector Reliability

PCB School

PCBA Press Fit Connector Reliability

Managing strain during press-fit connector insertion is essential for high-density PCB reliability. Discover best practices and how San Francisco Circuits ensures reliable assembly for HDI, mil-spec, and medical applications.

Read More

PCB Via Types

PCB School

PCB Via Types

San Francisco Circuits covers the 8 types of PCB vias including blind, buried, microvias, through-hole, stacked, & thermal vias - what they are, how they work, & where they’re used in advanced PCB design.

Read More

San Francisco Circuits, Inc.

1660 S Amphlett Blvd #200
San Mateo,CA 94402
Toll-Free: (800) 732-5143
E-mail: sales@sfcircuits.com

NIST Logo   cmmc level 2 certification   ITAR Compliance Seal  IPC International, Inc. Membership Seal

San Francisco Circuits - San Diego

3914 Murphy Canyon Rd., Suite A244
San Diego, CA 92123
Local: (858) 576-7202

Follow us

X Logo Facebook Logo LinkedIn Logo

©Copyright 2005 - 2026 - San Francisco Circuits, Inc. - All rights reserved

Latest News

09-14-2026

CMMC 2.0 Level II is Temporarily Suspended. Cybersecurity Compliance is Not.

The Department of War (DoW), formerly the Department of Defense, has temporarily suspended the planned Phase II rollout of the Cybersecurity Maturity Model Certification (CMMC) program, including the transition that would have made third-party C3PAO Level 2 assessments mandatory for applicable contracts and solicitations beginning November 10, 2026.

Read more

05-20-2026

San Francisco Circuits achieves CMMC Level 2 certification, confirming verified cybersecurity compliance for defense and aerospace supply chain partners.

Read more

User Login