Micro Circuits – HDI PCB



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Micro Circuits, a new technology offered by San Francisco Circuits, have some of the most advanced capabilities in arguably the fastest growing and most-requested PCB technology market, HDI printed circuit boards. HDI PCBs are circuits that offer much higher wiring densities per area than standard circuit boards, with finer lines and spaces, smaller vias and higher connection pad density.

The micro circuits fabrication opportunities offered by SFC’s portfolio of capabilities easily overcome the limitations found in standard circuit technologies through the utilization of ultra-thin cores, fine line processing and alternative via methods to reduce the size and weight of your components while simultaneously enhancing performance.

The HDI PCBs we offer include the following highly requested characteristics:

  • Blind and/or buried vias
  • Via-in-pad
  • Through vias from surface to surface
  • 20 µm circuit geometries
  • 30 µm dielectric layers
  • 50 µm laser vias
  • 125 µm bump pitch processing

Our high density circuit boards have the technology-pushing capabilities to drive applications in a large number of industries including but not limited to semiconductor test equipment, defense, medical and aerospace.

Call us at 800.SFC.5143 or get an instant PCB quote.

Multi Chip Module - HDI PCB

Multi Chip Module

High Density PCB Wirebond Array

High Density Wirebond Array

Fine Line PCB

8 Layer Flip Chip - HDI PCB

8 Layer Flip Chip

Benefits of HDI PCB Technology with Micro Circuits:

  • Shorter PCB manufacturing lead times and improved device performance for Flip Chip, BGA, MCM, SIP technologies and medical devices.
  • Allows utilization of technologies that require ultra thin cores, fine line geometries and alternative via technologies for enhanced thermal transfer in the case of a thermal PCB.
  • Allows utilization of the technologies that require 20um circuit geometries, 30um dielectric layers, 50um laser vias and 125um bump pitch processing.
  • Allows reducing the “time to market” equation by combining the process capabilities with a strong comprehension of high speed digital and high frequency RF PCB package requirements.
  • Increases the area for the PCB designer provider to place circuit components as the components are decreased in size and spaced much closer together. This also improves faster signal transmission and reduced signal loss.


  • High Tg, BT resins
  • Low Dk, Low Df Formulations
  • High Strength, Low CTE selections
  • Polyimide/Kapton
  • Multi-function FR-4
  • Min Cladding ¼ oz
  • Max Cladding 2 oz
  • Min Thickness .03mm (.0012)


  • Controlled Dielectrics Thicknesses
  • Controlled Impedance (2% tolerance)
  • Differential Signals
  • Microstrip and stripline
  • Build Ups (to 12 Layers)
  • Blind Vias, Buried Vias
  • Flex .025mm (.001)
  • Conductive Hole Plug
  • "Via in Pad" for RF and High Density substrates
  • Additive and Subtrative Processes


  • Mechanical, Laser and Plasma
  • Min drill hole .025mm (.001)


  • Wirebondable Structures
  • Differential Metalizations
  • Electrolytic/Electroless Plating
  • Full Body, Selective and Contact Gold
  • Immersion Silver


  • Min Line .020mm (.0008)
  • Min Space .020mm (.0008)
  • Finish Trace Tolerances +/-
    •  ¼ oz Int 5%
    •  1 oz Int 15%


  • Per IPC-SM-840
  • Taiyo and Conventional Epoxies
  • Liquid Photo-Imageable and Dry Films
  • "Flex" Mask


  • Complete COC’s
  • Cross Section Analysis
  • Bondability assurance
    (pull strength and sigma analysis)
  • XRF Analysis
  • NIST Certified


  • Gerber RS274X
  • DXF, DWG
  • AutoCAD


  • Valor Genesis 2000


  • High Density Flying Probes
  • Net List Comparison
  • AOI


  • OFHC Copper or 6061-T6 Aluminum
  • Conductive adhesives with precision
  • Cavity Fabrications


  • Thermal Stress/Cross Sections
  • Dielectric Spacing Verification
  • Plating Process Controls

We also specialize in flexible HDI PCBs which you can read more about on our flex PCB page and PCB assembly.

Thru Layer Visualization - HDI Circuit

Thru Layer Visualization

Last updated June 19, 2017